View VSC8201_2978857.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy without permission - page 1 of 21 - simpliphy ? VSC8201 pcb design and layout guide single port 10/100/1000base-t and 1000base-x phy introduction this purpose of this application note in conjunction with the VSC8201 datasheet is to provide information to assist in the desi gn and lay- out of the VSC8201 gigabit ethernet transceiver. power supply organiza tion and decoupling the VSC8201 requires a 3.3v and a 1.5v power supply source for operation using gmii, mii or tbi mac interfaces. in rgmii and rt bi modes, an additional 2.5v supply is needed as specified by the rgmi/rtbi standard. the VSC8201 can be powered using the followi ng options: ? 2 separate supplies, 3.3v and 1.5v respectively. ? a single 3.3v supply. this is done by using the optional on-chi p regulator control circuit, which drives a simple external ser ies pass type supply regulator (mosfet) to generate the 1.5v core power supply. pcb power plane organization it is recommended that the pcb pow er plane(s) in a system be divide d into four separate regions: power supply filtering and decoupling for best performance, each power supply region should contai n capacitors for both bulk decoupling and for local high-frequency decou- pling. this is summarized in the following tables: table 1: power supply plane regions pcb power plane description nominal supply voltage current a a. test conditions: room temperature (25 o c), 1000base-t data, full duplex, minimum ipg, 64- byte packets, rgmii mac active, excluding regulator power dissipation but including external twisted pair termination; al l worst case current figures have all nominal po wer supplies scaled by +5%. lqfp supply names b b. refer VSC8201 datasheet to correlate supply names with part pin numbers. typ max v+io digital input/output buffer supply 3.3v/2.5v 8ma 11ma vddio v+a33 filtered analog 3.3v supply 3.3v 101ma 111ma txvdd, vddrec33, vddpll33 v+a15 filtered analog 1.5v supply 1.5v 41ma 48ma vddrec15, vddpll15 v+dig digital core supply 1.5v 350ma 423ma vdddig
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 2 of 21 - the following figure shows the proposed layout for the local deco upling capacitors. the figure is approximately drawn to scale for stan- dard 0603 size capacitors. vias to the power and ground planes immediately in the vicinity of the capacitors provide a low indu ctive path and aid in heat dissipation. table 2: power supply decoupling for separate 3.3v and 1.5v power supplies pcb power plane bulk decoupling required local decoupling required v+io 1 pair of 22uf, 1uf four 0.1uf capacitors v+a33 1 pair of 22uf, 1uf and 1 10uf two 0.1 uf capacitors v+a15 1 pair of 2.2uf, 1uf one 0.1 uf capacitor v+dig 1 pair of 22uf, 1uf four 0.1uf capacitors table 3: power supply decoupling for single 3.3v supply and optional fixed 1.5v regulator pcb power plane bulk decoupling required local decoupling required v+io 1 pair of 22uf, 1uf four 0.1uf capacitors v+a33 1 pair of 22uf, 1uf and 1 10 uf two 0.1uf capacitors v+a15 1 pair of 2.2uf, 1uf one 0.1 uf capacitor v+dig 2.2uf four 0.1uf capacitors VSC8201 128 lqfp (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 note:place vias close to or under neath the capacitor pads for low inductive path and higher heat dissipation rate. 0.1 uf figure 1: local high-frequency decoupling capacitor layout - lqfp package
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 3 of 21 - in addition, a ferrite bead should be used to isolate each analog supply from the rest of the board. the bead should be placed in series between the bulk decoupling capacitors and the local decoupling capacitors. figure 3: power supply decoupling schematic the beads should be chosen to have the following characteristics: ? current rating of at least 150% of the maximum current of the power supply. ? impedance of 80 to 100w at 100mhz. recommended beads are: ? panasonic excelsa39 or similar. ? steward hi 1206n101r-00 or similar. note:place vias close to or under neath the capacitor pads for low inductive path and higher heat dissipation rate. 0.1 uf . a b c 12 3 4 56 789 10 f k j h g e d figure 2: local high-frequency decoupling capacitor layout - lbga package
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 4 of 21 - since all pcb designs yield unique noise coupling behavior, not all ferrite beads or decoupling capacitors may be needed for ev ery design. for this reason, it is recommended that system designers provide and option to replace th e ferrite beads with zero-ohm resistors, once thorough evaluation of system performance is completed. pcb chassis ground region to isolate the board from the esd events and to provide a common-mode noise ground path, a separate chassis ground region shoul d be allocated. this should provide an electrical connection to the external chassis and the shield ground to discharge common-mo de noise through a 75-ohm resistor and a single 1000pf 2kv capa citor. see ?VSC8201 system schematic? in the datasheet. figure 4: ground plane layout key points ? the chassis ground and the pcb ground should have as much se paration as possible. 45 mils or greater is recommended. ? there should be no power or ground plane beneath th e primary and secondary coils of the transformer.
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 5 of 21 - regulator circuit for systems with a single power supply, the VSC8201 provides an option to generate the 1.5v supply from the 3.3v supply by usin g the on chip regulator. the internal regulator is enabled by having a 10k pull-up on the reg_en pin. to use the regulator the following additional components are required: ? fet device, similar to fairchild fdt439n. ? for decoupling, two 0.0047uf capacitors with 10% tolera nce or better. npo, x7r or x5r are all acceptable. systems with single 3.3v,+/-10% wake on lan supply the following figure shows the circuit for generat ing the 1.5v supply using a 3.3v,+/-10% supply figure 5: regulator circuit using 3.3v, +/-10% supply key points ? place a 0.0047uf capacitor as close to reg_out as possible. ? place a 0.0047uf capacitor as close to the fet as possible. ? tie the gnd line together with vrefn, capa citor connected to ref_filt, resistor r4 (see figure above) and then connect to a co m- mon ground. ? vrefp should be connected to the analog 3.3v plane i.e. v+a33. using actiphy tm power management the VSC8201 supports a new power saving mode called actiphy tm , particularly suited to power saving applications like laptop comput- ers with wake on lan capability. 1 when in actiphy tm mode the phy is in one of two power down states and has the ability to detect valid signal energy levels at the media pins and convey it to the station manager. 1. refer VSC8201 datasheet.
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 6 of 21 - the following tasks are required to be done by the station manager to use the power saving actiphy tm feature: 1. setting the squelch level: as per ieee standard 802.3 mii register 22:11 and 22:10 set the s quelch levels for 10base-t operation. in addition to the 10bas e- t squelch level control, the VSC8201 uses these bits to control the actiphy tm squelch levels. this is summarized in the following table: 2. enabling the interrupt pin: the VSC8201 conveys the valid signal detect signal via the mdint# pin. in order to enable the mdint# pin the station manager must set the mii register 25:15. 3. enabling the actiphy tm signal detect interrupt: in actiphy tm mode mii register 25:13 i.e. the link state-c hange interrupt mask also acts as the actiphy tm signal detect interrupt mask. this bit should be set to enable the actiphy tm signal detect interrupt. when a valid signal level is detected an interrupt occurs and register 26:13 is set by the VSC8201 phy. the mdint# pin is pulled low. 4. setting the phy in actiphy tm mode: the station manager can put the VSC8201 in actiphy tm mode by setting mii register 23:5. on setting register 23:5 the phy goes in one of the following power down states dep ending upon the state of the mii register 18:0 5. coming out of actiphy tm mode: the station manager responds to the in terrupt signal by clearing the actiphy tm enable bit i.e. clears the register 23:5. when this bit is cleared, all blocks of the phy are powered up and the phy re verts back to auto-negotiation and tries to establish a link. th e sta- tion manager should read mii register 26 to reset the interrupt status register. table 4: 10base-t/actiphy tm squelch levels register bit setting 22:11:10 10base-t/actiphy tm squelch level 00 normal squelch 01 low squelch 10 high squelch 11 reserved table 5: register bit setting 18:0 power down state power dissipation a a. power dissipation figures are currently unavailable. 0 pll disabled - 125mhz clock not available on clk125 pin 1 pll enabled - 125mhz clock available on clk125 pin
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 7 of 21 - design for signal integrity many high speed signal pins on the VSC8201 have rise/fall times of the order of 0.7 to 2.4 ns. be cause of these fast rise/fall times, inter- connects should be treated as transmission lines rather than simp le lumped element connections. use of transmission lines with a basic understanding of line matching will reduce signal reflecti ons which degrades overall performance of the part. theory in order to apply correct impedance matching/termination techniqu es it is important to know about the types of interconnects us ed on the pc board. there are 2 kinds of traces on a pc board. ? in case the signal transmission line is sandwiched between the diel ectric material of the board and 2 conducting planes it is called a stripline. figure 6: transmission lines ? a signal transmission line that has one side open to air and dielectric material and a conducting plane beneath it, is called a micros- trip. impedance of a transmission line is determined by the relative diel ectric constant of the pc board material, thickness of the dielectric ,the width and the thickness of the transmission line . characteristic impedance of the microstrip is calculated using the approximation: the propagation delay for the microstrip is: r hw t z o 87 r 1.41 + ------------------------- 5.98 h ? 0.8 wt + ------------------- ? ln ? = t pd 85 () 0.475 r 0.67 + ps/ft ? =
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 8 of 21 - characteristic impedance of the strip line is calculated using the equation : where is the distance between the planes above and below the stri pline. the above formula is used when the stripline is equid istant from the above and below planes. the propagation delay of the strip line is: if the length of the line such that: then the line must be considered a transmission lin e and proper termination techniques be employed. assuming a dielectric constant of 4.4 for fr-4, we get =141ps fo r a microstrip line. if the rise time of the signal is 0.7ns th en a trace with length l greater the 0. 827 inch should be considered a transmission line. the 2 most common termination techniques are as follows: ? place a resistor equal to the characterist ic impedance of the line in series with and close to the signal source. this is call ed series termination or source termination. ? place a resistor equal to the characterist ic impedance of the line between ground and the end of the signal trace. this is cal led end termination. the common value for the characteristic impedance of a transmission line is 50 . z o 60 r -------- - 4 b ? 0.67 0.8 wt + () ------------------- ------------------- - ? ln ? = b t pd 85 () r ps/in ? = l lin () rise time ps () ? propagation delay ps inch ---------- - ?? ?? ? ------------------------- ------------------------------ ---------------- 1 6 -- - < t pd ?
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 9 of 21 - high speed signals of VSC8201 figure 7: VSC8201 system schematic u2 mac controller u3 jtag port controller u4 station manager cpu and/or control logic t1 pulse h5008 u1 VSC8201 mdc mdint# rst# pwdn# tdi tms tck trst# txvp_a txip_a txin_a txvn_a pllmode xtal1/refclk 47.5 (1%) 47.5 (1%) 47.5 (1%) 47.5 (1%) 47.5 (1%) 47.5 (1%) 47.5 (1%) 47.5 (1%) 1 2 3 6 4 5 7 8 j1 rj-45 a+ a- b+ b- c+ c- d+ d- s1 s2 col crs rx_clk rx_dv rx_er rxd[7] rxd[6] rxd[5] rxd[4] rxd[3] rxd[2] rxd[1] rxd[0] tdi tdo tms tck trst# clk125mhz 2k v+io gtx_clk tx_er tx_en txd[7] txd[6] txd[5] txd[4] txd[3] txd[2] txd[1] txd[0] reset# pwdn mdc mdio mdint# 0.1f 0.1f 0.1f 0.1f 1000pf, 2kv 3.3v 3.3v 3.3v gtx_clk tx_er tx_en txd[7] txd[6] txd[5] txd[4] txd[3] txd[2] txd[1] txd[0] txvp_b txip_b txin_b txvn_b txvp_c txip_c txin_c txvn_c txvp_d txip_d txin_d txvn_d 9 10 v+io vddio vdddig v+a33 txvdd vddrec33 vddpll33 v+a15 vddrec15 vddpll15 digital i/o digital core (fixed or optionally regulated) analog analog ref_filt ref_rext gnd vrefn* reg_out r t r t r t r t v+dig gnd col 50 rxd[7] 50 rxd[6] 50 crs 50 rxd[5] 50 rxd[4] 50 rxd[3] 50 rxd[2] 50 rxd[1] 50 rxd[0] 50 rx_clk 50 rx_dv 50 rx_er 50 r t r t r t r t r t r t r t gnd 75 75 75 75 tx_clk (used for mii & tbi modes only) gnd common analog / digital ground plane 50 tx_clk (used in mii & tbi modes only) * see next page 1f reg_en/ quality xtal2 25mhz gnd 33pf gnd 33pf vrefp* 1f v+a33 * vrefp and vrefn should use separate traces to the 3.3v power regulator output and ground. this avoids any bus drops which would cause inaccuracy in the reference voltage leave floating for normal operation phy addressing: this circuitry is used when all phy address bits = 0. 50 50 50 50 addr(0) / link10 addr(1) / link100 addr(2) / link1000 addr(3) / duplex r r r r r link100 link1000 duplex activity mode1000 nc mode100 nc mode10 nc aneg_dis nc frc_dplx nc addr(4) / activity 50 osc_en / clk125 50 10k v+io 10k v+io tdo 50 mdio 50 notes: 1) darkened transmission lines indicate 50-ohm microstrips. 50 gnd gnd link10 reg_en / quality: this circuitry is used when the regulator is not enabled. vssref 2.26k (1%) r quality
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 10 of 21 - mac transmit and receive interface pins these signals on these pins have rise/fall times of about 0.7 to 1 ns. to adequately accommodate these signals on a pcb, it is recom- mended that the traces be designe d as either a microstrip or stripline transm ission lines with a charac teristic impedance of 50 . it is also important that an unbroken ground plane exist above and/or below these signals. for the mac transmit interface, if the output resistance of t he corresponding pins on the mac side is less than 50 , additional series termination resistor should be placed close to the mac device. for the VSC8201 mac receive interface, each pin is self-calibrating to an output resistance of 50 . thus, external series termin ation resistors are not required as long as the c haracteristic impedance of the trace is 50 . as shown in the previous section, for a ri se time of 0.7 ns, the minimum length of a microstrip for it to be considered a trans mission line is 0.827 inches (for standard fr4 material with dielectric c onstant of 4.4). hence above mentioned series termination consider ations are important only if the microstrip leng th is greater than 0.827 inches. for most cases the mac can be placed close to the phy?s mac interface pins. twisted-pair interface pins as the interface to external cat-5 cable, these pins are orga nized in four differential pairs for each port.these are labelled ?txip_x? and ?txin_x?, where ?x? is the particular pair within a single cable. when routing these pairs on a pcb, they must be routed using transmis- sion lines with a characteristic impedance of 50 , and the traces fo r each differential pair must be routed symmetrically as clo se to each other as possible. by keeping the differential pairs together on the board, the result is the required 100-ohm differential imp edance for each twisted pair. other impedance controlled pins the following signals have 50 ohm integrated series termination re sistors and therefore should be routed using 50 transmission lines: ? addr(0)/link10 ? addr(1)/link100 ? addr(2)/link1000 ? addr(3)/duplex ? addr(4)/activity ?mode10 ?mode100 ? mode1000 ?tdo ? osc_en/clk125 ? reg_en/quality ?mdio other board layout considerations ? place the rj-45, transforme r and the phy device as close as possible to each other. ? all traces that run from the transformer to the rj-45 sh ould be matched in length and be as short as possible. ? keep a continuous ground plane underneath t he high speed mac tx/rx data signal traces. these traces should be of equal length and be as short as possible. ? ? ? ? ? ?
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 11 of 21 - special rgmii implementation using a single 3.3v supply this section addresses designers who wish to use the VSC8201 si ngle port gigabit ethernet phy in rgmii interface mode at an int er- face voltage of 3.3v, rather than the standard 1 2.5v. VSC8201?s rgmii interface description the VSC8201 phy is designed, as per the rgmii version 1.2a spec ification, to support rgmii operation at a 2.5v i/o supply. in addition to the rgmii requirements specified by the standard, the phy also has an internal clock delay feature (enabled by setting mii r egister 23.8) that adds an internal delay of ~2ns to the rxc and the txc signals when operating at 2.5v . this feature eliminates the ne ed for pcb trace delays or 2ns buffers in the path of the rxc and txc traces. due to customer interest in using the VSC8201 phy in rgmii inte rface mode with a single 3.3v supply, vitesse has characterized the rgmii i/o timing of the phy under this condi tion in the following two configurations: ? standard rgmii implementation (i.e. with rxc and txc trace delays on the pcb) ? rgmii implementation using the internal clock delay feature. since the VSC8201 phy was not specifically designed for rgmii operation with a 3.3v i/ o supply, certain accommodations must be made to the board layout in order to ensure a robust interface. the VSC8201 phy complies with the i/o timing requirements spec ified in the rgmii version 1.2a specif ication. no special board layout considerations other than those mentioned in the standard are req uired for this implementation. rgmii implementation using the internal clock delay feature with 3.3v i/o supply with a 3.3v i/o supply, the worst case internal delay added to the txc signal is around 3ns. if the txc, td[3:0], and tx_ctl tr aces are length matched on the pcb, then the phy may mis-latch data under the worst case txc delay condit ions, resulting in packet error s at the mac/phy transmit interface. due to this it is important to follow the guidelines mentioned in the section below during boar d layout. 1. rgmii version 1.2a
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 12 of 21 - rgmii single 3.3v supply implementation methods method i - standard rgmii implementation in this mode the internal clo ck delay feature of the phy is not enabled. see mii register 23.8 for more information. board layout benefits ? does not require an external 2.5v suppl y, thereby reducing overall system cost. drawbacks ? needs extra board space for the additional trace delays on the rxc and txc traces. mac VSC8201 tx_ctl td0 td1 td2 td3 rd0 rd1 rd2 rd3 rx_ctl txc rxc 1.5ns-2ns pcb trace additional pcb trace delay 1.5ns-2ns pcb trace additional pcb trace delay vddio=3.0 - 3.6v vddio=3.0 - 3.6v
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 13 of 21 - method ii - rgmii implemen tation using the internal clock delay feature in this mode the internal clock delay featur e is used i.e. mii register bit 23.8 is set. board layout benefits ? does not require an external 2.5v supply, thereby reducing system cost. ? does not require any additional delays on the txc and rxc traces. drawbacks ? needs extra board space for the additional trace delays needed on the td[3:0] and the tx_ctl traces. mac VSC8201 rd0 rd1 rd2 rd3 rx_ctl td3 rxc 700ps of additional trace delay w.r.t txc vddio=3.0 - 3.6v vddio=3.0 - 3.6v td2 td1 td0 tx_ctl txc
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 14 of 21 - method iii - rgmii implem entation using the internal clock delay feat ure with locally generated 2.5v i/o supply in this mode the internal clock delay featur e is used i.e. mii register bit 23.8 is set. board layout benefits ? does not require an external 2.5v supply, thereby reducing system cost. ? does not require any additional delays on the txc and rxc traces. drawbacks ? requires a diode and a resistor. ? the mac which is at 3.3v should be capable of detecting 2.5v logic levels. mac VSC8201 rd0 rd1 rd2 rd3 rx_ctl td3 rxc vddio_mac=3.15 - 3.45v vddio_phy td2 td1 td0 tx_ctl txc vddio_phy vddio_mac=3.15 - 3.45v 1n914 ma2j111 ma111 or equivalent 470 ohms 0.1uf 0.001uf
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 15 of 21 - led/address circuit the following pins of the VSC8201 are input/output pins: ? addr(4)/activity ? addr(3)/duplex ? addr(2)/link1000 ? addr(1)/link100 ? addr(0)/link10 ? reg_en/quality in input mode these pins are sampled on the rising edge of rst# signal. after reset these are in output mode.the addr and reg_e n pins sampled at startup determine th e polarity of the led output signal. the quality led is asserted when the signal quality is good. figure 8: led interface circuit
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 16 of 21 - serial management interface the VSC8201 contains a standard serial managem ent interface (smi) as defined by ieee st andards. this interface consists of the fol- lowing signals: it is important to note that both mdio and mdint# signals are co nfigured as open drain, and thus require an external pullup res istor. only a single pullup resistor on each signal is needed for the sys tem, regardless of the number of devices. for mdint# a single 10kohm system pullup resistor is sufficient. unlike mdint#, the value of the pullup needed for mdio must be c hosen to match the characteristics of the system. of critical i mpor- tance is the rise time needed to charge the total capacitive load on the mdio up to logic ?1? through the pullup resistor. this constant is defined simply as: in most cases the number of devices on the bus will be 1. but in the case where more devices are added to the bus, the rise tim e increases due to the increased bus capacitance. in order to lowe r the rise time, a smaller resistor value must be used. however , if too small of a value is used, devices will be unable to transition th e bus to a logic ?0?. this occurs when the current sinking cap ability of the pins in a logic ?0? state is exceeded. for the VSC8201, the mdio input capacitance is 5pf, and the maximum current sinking capa city is 10ma. typical values are given below: ? for mdc frequencies of 2.5mhz a nd below, a 2k pullup resistor should suffice fo r most applications.this assumes the input capa ci- tance of each device is between 5-1 0pf and that each device can sink 1. 65ma of current in the mdio pin. ? for faster mdc frequencies (>2.5mhz), a sm aller pullup is necessary. the smallest recommended pullup resistor for use with the VSC8201 is 470 . table 6: serial management interface pins signal name type description mdc input management data clock. a 0 to 25mhz reference input used to clock serial mdio data into and out of the VSC8201. the expected nominal fr equency is 2.5mhz, as specified by the ieee standard. this clock is typica lly asynchronous with respect to the phy?s transmit or receive clock. mdio open drain management data i/o. mdio configuration and status data is exchanged on this pin bidirec- tionally between the phy and the station manager, synchronously to the rising edge of mdc. this pin normally requires a 1.5k ? to 2k ? external pull-up resistor at the station manager. the value of the pull-up resistor depends on the md c clock frequency and the maximum capacitive load on the mdio pin. mdint# open drain management data interrupt output. this open drain, active low output signal indicates a change in the phy?s link operating conditions fo r which a station manager must interrogate to determine further information. this pin should be pulled up to vddio at the station manager or controller through an external 10k ? pull-up resistor. r pu c total = ?
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 17 of 21 - rj-45 connectors and magnetic modules rj-45 connector recommendations system designers can choose either the tab-up or tab-down connectors. leds can also be integrated into the connectors. figure 9: rj45 connectors due to the orientation, the pinouts of the tab-up and the tab- down are reversed. the VSC8201 will work equally well using eithe r orienta- tion. the tab-down connector is more wide-spread than the tab-up connector in the nic card industry. cat-5 vs. cat-3 connectors when utilizing 1000base-t or 100base-t, it is important that ?cat-5? rj-45 connectors be used as opposed to ?cat-3?. this refer s to the amount of cross-talk between wir e pairs within the connector. in addition to the electrical characteristics, some manufact urers have two options for the connector pinout. these are typicall y labeled as ?standard? and ?cat-5?. this is not to be confused with the electr ical specification for the connec tor. thus, two versions of a cat-5 rj-45 connector are available: one with ?standard? pinout and one with a ?cat-5? pinout: figure 10: rj45 connector pinouts specific rj-45 recommendations virtually any rj-45 connector that meets the cat-5 electrical specification will work with the VSC8201. two such manufacturers are: amp (a division of tyco international, ltd.) tel: 717-564-0100 http://www.amp.com transpower technologies, inc. tel: 775-852-0140 http://www.tra ns-power.com
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 18 of 21 - magnetic modules for best performance, proper magnetic modules must be used wit h the VSC8201. in addition, some companies integrate the magnetic modules into the rj-45 connector. note on return-loss compensation circuit: testing has indicated that some magnetic modules may not pass the ieee specification for return loss. in these cases, an extra resistor-capacitor circuit can be added for each of the sub-channels. see ?return lo ss circuit for pulse h5008 transformer? on page 18. the presenc e of this circuit serves only to allow the system to pass i eee return loss measu re- ments and does not affect the performance of the phy in any othe r way. the exact values required for the resistors and capacit ors var- ies according to each manufacturer and can be foun d in table 8: ?recommended magnetic modules.? figure 11: return loss circuit for pulse h5008 transformer below is a list of recommended magnetic modules: table 7: sample part numbers for rj45 connectors part number manufacturer description 558341-1 amp single port, unshielded, without leds, tab-down, ?cat-5? pinout. rj7g02 transpower tech., inc. single port, through hole, tab-up, pinout is unique to transpower rj7g07 transpower tech., inc. a a. this module has an integrated magnetic module single port, through hole, tab-up, pinout is unique to transpower pulse engineering, inc. tel: 858-674-8100 http://www.pulseeng.com halo electronics, inc. tel: 650-568-5800 http://www.haloelectronics.com delta electronics, inc. tel: http://www.delta.com.tw/products/networking.asp
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 19 of 21 - thermal performance figure 12: heat dissipating path for ic packages the two paths of heat dissipation show n in the above figure are as follows: 1. ic chip package atmosphere 2. ic chip package lead pc board atmosphere the amount of heat dissipated by path 2. depends on various fact ors like pad size, wired length, layer configuration, thickness , materials etc. of the pc board but, typically, 10% to 50% of the heat is dissipat ed through the pc board. although low power consumption of the VSC8201 el iminates the need of external heatsinks or fans in most designs, it is always r ecom- mended to follow certain guidelines for adequate heat dissipation. for proper operation of the VSC8201, a silicon junction temperature equal to or below 125 o c must be maintained for commercial temperature ranges. within the constraints of the commercial te mperature range, the limits for junction-to -ambient thermal resi stance are as follows: 1 where = junction to ambient thermal resistance, = junction temperature, table 8: recommended magnetic modules part number manufacturer description return loss compensation lf9207a delta single-port, surface mount h5008 pulse single-port, surface mount c 1 , c 4 = 10pf, c 2 = 6.8pf s558-5999-p3 bel single-port, surface mount tg1g-s002nz halo single-port, surface mount gb2g04 transpower single-port, surface mount 1. the actual of the VSC8201?s 128 lqfp and the 100 ball lbga package is approx. 30 o c/w to 35 o c/w. this yields a t j ja p dmax () 125 70 o c ? () 35 o cw ? () () ? 1.5 w for t j 125 o c () == ja commercial () t j t a ? p d ---------------- - 125 o c 70 o c ? 1 w -------------------- -------------- - 55 o cw ? () == = ja t j
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 20 of 21 - = ambient temperature, = power dissipation. for the 128 pin lqfp vias which connect the nearby high frequen cy decoupling capacitors to the ground and power planes are suff icient for the required heat dissipation rate. see ?local high-frequency decoupling capacitor layout - lqfp package? on page 2. for proper cooling of the 100 ball lbga, a pcb via must be placed bet ween the thermal bga ball pads in a checkerboard pattern ( see figure 13: ?thermal via layout?, below). each of these ?thermal vias? should then be ro uted to the bga ball pads near it with a wide trace or solid copper fill to increase the conductive area on th e surface of the pcb. in order to dissipate heat below the bga package, the pcb thermal vias must connect to a solid ground plane within t he board. it is recommended that the ground plane have a minimum thick- ness of one ounce (see figure 14: ?therm al ground plane connections?, below). t a p d bga ball pad pcb thermal via pcb traces figure 13: thermal via layout VSC8201 bga package bga balls 1-ounce ground plane thermal via figure 14: thermal ground plane connections
VSC8201dl rev. 1.6.3 - 9/29/04 vitesse - confidential & proprietary - do not copy wi thout permission - page 21 of 21 - document history & notices revision number date description 1.6.1 16 jan 03 1.6.2 7 aug 03 updated decoupling power supply, capacitor lay- out (added lbga figure), and schematic 1.6.3 29 sep 04 changed cis8201 to VSC8201 globally. integrated the informat ion from the cis8201 rgmii 3.3v appnote into this document. proprietary and confidential: all of the information included herein, as well as any oral or wr itten discussions regarding such information and any materials generated as a result of such discussions, is confidential information that is proprietary to vitesse semicon ductor corporation and should be used by its recipient so lely as authorized by vitesse semiconductor corporation under written non-disclosure agreemen t. this errata is subject to change without notice. vitesse reserves the right to make changes to the product(s) or information co ntained herein in order to improve the product in any manner. no liabi lity is assumed as the result of the use or application of any product or informatio n contained within this or related documents. vitesse does not convey patent rights, nor thos e of others, from the sale or use of the products described o r referenced within this document. ?simpliphy?, ?microphy?, ?veriphy?, and ?a ctiphy? are trademarks of vitesse semic onductor corporation. all third-party brand an d product names within this document are trademarks or regist ered trademarks of their respective owners. ? copyright 2003-2004 by vitesse semiconductor corporation all rights reserved.

▲Up To Search▲

Price & Availability of VSC8201

	To Download VSC8201 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .